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广东赛微微电子股份有限公司
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    • Layout Engineer
    • Shanghai
    • 2020-12-01

    Job Description:

    1.   Assist in estimating the chip area under the guidance of the layout leader;

    2.    Carry out module layout design according to circuit design;

    3.   Conduct DRC and LVS checks on the layout design;

    4.   Study the design rules to avoid ESD, latch-up effects and other parasitic effects;

    5.   Help the designers to complete the post-layout simulation.

    Job Requirements:

    1.   Bachelor degree or above in microelectronics, electronics and other related majors, with more than 2 years of relevant working experience;

    2.   Rich knowledge of layout, familiar with layout design. Understand the matching and parasitic factors in layout design;

    3.   Experienced in Cadence layout environment and Calibre verification tools;

    4.   Good communication skills and strong teamwork spirit.


    Send your resum to: hrcw@cellwise-semi.com

    • IC Design Engineer
    • Shanghai
    • 2020-12-01

    Job Description:

    1.    Conduct technical feasibility study of the new projects, according to the marketing requests.

    2.    Design and simulate of analog circuit blocks or the small and medium-sized chips according to the spec;

    3.    Conduct DFMEA analysis on product design and provide improvement plans when necessary;

    4.    Provide design guidance for layout design engineers, and run the post-layout simulation when necessary;

    5.    Provide chip function verification plan, verify and debug engineering samples;

    6.    Assist the test engineer to complete the mass production test plan;

    7.    Prepare design documents, apply for patents or publish papers for innovative designs.

    Job Requirements:

    1.   Master degree or above in microelectronics, electronics and other related majors with more than 2 years of relevant work experience, or bachelor degree with more than 4 years of relevant work experience;

    2.   Solid theoretical knowledge of analog circuits, and be familiar in the design skills of ADCs, amplifiers, bandgap and other commonly used analog modules;

    3.   Experienced in Cadence design environment and simulation tools such as Spectre, Hspice and Eldo;

    4.   Have knowledge of DFMEA;

    5.   Have strong learning ability, analytical ability, communication ability and a good team spirit;

    6.   Fluent in English reading and writing.


    Send your resume to :hrcw@cellwise-semi.com

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